1. Field of the Invention
The present invention generally relates to integrated circuit structures that include multiple height devices and more particularly to an improved structure that reduces the height of the passivating layer to reduce the height of the contacts made to such devices.
2. Description of the Related Art
Fabrication of BiCMOS chips (integrated circuit chips having both bipolar transistors and complementary metal oxide semiconductor (CMOS) transistors) requires process integration of both bipolar and CMOS field effect transistors (FET) devices. One of the key challenges in process integration is to make contact connections to the differently sized devices. Reliable contact connection has always been one of the significant issues for base CMOS FET fabrication. Due to the significant vertical height difference between bipolar and CMOS FET devices, contact formation becomes even more difficult for BiCMOS chip fabrication. At present, the aspect ratio of contacts for BiCMOS is about 30% higher than base CMOS for 0.25 and 0.18 um SiGe technologies. This aspect ratio difference becomes unsustainable for future SiGe technologies (e.g., 0.13 um or below). The present invention described below provides a reliable solution to contact formation for future BiCMOS technologies.